As the complexity of integrated circuits (ICs) increases and access to their internal circuit nodes becomes harder, properly testing such devices becomes a major bottleneck during their prototyping, development, production, and maintenance. As a result, designs with BIST implementation have become commonplace. In a BIST implementation, circuitry (which is intended solely to support testing) is included in an IC or in a system including ICs.
With 64-bit support in the latest generation of microprocessor families, it is customary to find large (e.g., up to 40 GB) external memories and associated interconnects. Although the memory providers normally guarantee a reasonably high level of test coverage before shipping the memory chips to their customers, it is common to find defects in the memory chips after they are mounted on boards or modules. As a result, some memory tests need to be done on the system to detect defects that either remained undetected due to gaps in the manufacturer's test process or were introduced during the board or module manufacturing process.
Another category of failures can be attributed to interconnect defects. These defects fall into two categories:                direct current (DC) or stuck type failures that can be tested through boundary scan if the external memory is compliant with the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard, and        alternating current (AC) failures that cannot be tested through conventional boundary scan.        
Collective experience in the industry indicates that interconnect defects in general, and specifically memory interconnects, contribute significantly to failures on boards, modules and systems. This trend is further exacerbated by new memory access paradigms such as GHz speeds of memory IOs, double data rate (DDR) memories, and wave pipelining on memory interconnects. Hence, it is becoming necessary to apply in-situ tests on boards and systems that specifically target interconnect to memories.
Current board and system test strategies often rely on standard “invasive” test techniques involving either “Bed of Nails” or OBN type probing, or a “Hot Mock Up” type interconnection technique. These different methods of testing enable the physical “stitching” together of a system to allow booting to the local operating system (OS) or test kernel. Once the system has booted, diagnostic testing can proceed. However, with the escalation of board operating frequencies and bus speeds at the connectors (sometimes reaching 150 MHz and beyond), the “stitching” introduces signal integrity or timing issues that render these techniques often unreliable or non-repeatable. This fundamental problem results in higher test costs due to higher manufacturing retest rates, higher no-trouble found (NTF) rates, and/or higher test capital consumption.
A solution can be using power-on self-test (POST). However, an important prerequisite for using POST is a functional and reliable central processing unit (CPU) and a programmable read-only memory (PROM) boot path. To fulfill this requirement, the functionality and integrity of several parts of the chip or module (such as PROM, bus interface, peripheral component interface (PCI) bus) have to be assured first. This, in turn, requires a significant investment in expensive test hardware and test fixture capital.
Furthermore, while POST can be utilized as a board system level test feature, any enhancement to POST requires significant development time and cost. This, along with the fact that POST development requires a “golden” board as a precondition, makes it logistically difficult to rely completely on POST enhancements to cover memory and memory interconnect test and diagnosis. Consequently, the test infrastructure (test host, instrumentation, fixtures, etc.) costs have quadrupled from last generation to the current generation of product testing. This increase in test costs has necessitated some fundamental changes in testing strategies for external memories and other board or system level components. This change has mainly been in the form of an increased reliance on embedded and structured test methodologies that are independent of the OS and require only a minimal set of system level resources (power, clocks, and the IEEE 1149.1 standard interface) to be functional.
External memory BIST (EBIST) is one such methodology. Not having to boot to a local OS relieves the requirement of having to “stitch” together a system with costly or unreliable invasive probing or interconnection techniques. But having a memory test is not sufficient. The interconnect between a chip and associated external memories must be tested as well. The common way for testing for DC faults is through IEEE 1149.1 boundary scans. However, for example, today's DDR memories are usually not IEEE 1149.1 compliant and interconnects between such memories and other chips on a system or board are not tested well.
Memory BIST is used today in the industry for testing embedded memories (such as that available commercially from Logic Vision of San Jose, Calif. Such solutions are generally based on hard-coding a predefined test algorithm and data patterns. Another approach is based on multiplexing EBIST logic into the memory bus input/outputs (IOs), thus bypassing all internal logic. With advances in technology and processes, and a wide range of available memory designs, however, there is an increasing need for more flexibility in the kind of test algorithms and the test patterns.
To address this issue, one proposed approach is to implement a processor-based engine with two separate instruction storage memories. This approach offers a fair degree of flexibility but suffers from high area overhead. Another proposed approach is implementing an EBIST that reduces area overhead by coding BIST features into register transfer level (RTL). However, this approach results in less flexibility of test algorithms and may not be applicable to many memory chips available on the market today. Some of the issues with past EBIST techniques can be summarized as follows: (a) they require intrusion at a chip's IOs, which are usually in the critical paths, resulting in timing problems and design iterations to accommodate EBIST; (b) they require reimplementing the random access memory (RAM) access protocol inside the BIST engine, resulting in unnecessary area overhead (not to mention the risk of implementing and, hence, testing an incorrect protocol); and/or (c) they generally hardcode the test algorithm, the data background, and/or both, resulting in low test coverage of the memory subsystem and not providing the flexibility required for diagnosis or for targeting memories from different vendors.